The present invention relates to a capacitor for semiconductor memory device and a method of manufacturing he same, and more particularly to a capacitor for semiconductor memory device including a conductive barrier having an excellent step coverage, between a dielectric layer and an upper electrode and a method of manufacturing the same.
As the number of memory cells composing DRAM semiconductor device has been recently increased, occupancy area of each memory cell is gradually decreased. Meanwhile, capacitors formed in the respective memory cells require a sufficient capacitance for precise reading out of storage data. Accordingly, the current DRAM semiconductor device requires memory cells in which capacitors having larger capacitance as well as occupying small area are formed. The capacitance of a capacitor can be increased by using an insulator having high dielectric constant as a dielectric layer, or by enlarging the surface area of a lower electrode. In a highly integrated DRAM semiconductor device, a Ta2O5 layer having a higher dielectric constant than that of the nitride-oxide(NO) is now used as a dielectric, thereby forming a lower electrode of a 3-Dimentional structure.
FIG. 1 is a cross-sectional view showing a capacitor for a conventional semiconductor memory device. Referring to FIG. 1, a gate electrode 13 including a gate insulating layer 12 at a lower portion thereof is formed according to a known technique on the upper part of a semiconductor substrate 10 which a field oxide layer 11 is formed at a selected portion thereof. A junction region 14 is formed on the semiconductor substrate 10 at both sides of the gate electrode 13, thereby forming an MOS transistor. A first interlayer insulating layer 16 and a second interlayer insulating layer 18 are formed on the upper part of the semiconductor substrate 10 which the MOS transistor is formed therein. A storage node contact hole h is formed inside the first and the second interlayer insulating layers 16,18 so that the junction region 14 is exposed. A cylinder type lower electrode 20 is formed according to a known method, inside the storage node contact hole h so as to be in contact with the exposed junction region 14. A HSG(hemi-spherical grain) layer 21 is formed on a surface of a lower electrode 20 to increase the surface area of the lower electrode 20 more. A Ta2O5 layer 22 is deposited on the upper part of the lower electrode 20 which the HSG layer 21 is formed thereon. The Ta2O5 layer 22 can be formed according to PECVD(plasma enhanced chemical vapor deposition) method or LPCVD(low pressure chemical vapor deposition) method. At this time, the Ta2O5 formed according to the PECVD method has an advantage of excellent layer quality, but a disadvantage of poor step coverage property. Therefore, the conventional Ta2O5 layer 22 has been formed according to the LPCVD method having an excellent step coverage property. Afterwards, Ta2O5 layer 22 is crystallized after a selected thermal process. A titanium nitride layer(TiN) 23 serving as the conductive barrier is formed on the upper part of the Ta2O5 layer 22. The TiN layer 22 is formed according to the LPCVD method or a sputtering method. An upper electrode 24 made of a doped polysilicon layer is formed on the upper part of the TiN layer.
However, the capacitor using the Ta2O5 layer as a dielectric has the following problems.
First, a difference in the composition rate of Ta and O is generated since the Ta2O5 layer 23 generally has unstable stoichiometry. As a result, substitutional Ta atoms, i.e. vacancy atoms are generated in a thin film. Since those vacancy atoms are oxygen vacancies, leakage current is generated. The amount of vacancy atoms can be controlled depending on the contents and the bonding strength of components in the Ta2O5 layer; however, it is difficult to eliminate them completely. To stabilize the unstable stoichiometry of the Ta2O5 layer, the Ta2O5 layer is oxidized so as to remove the substitutional Ta atoms therein. However, when the Ta2O5 layer is oxidized to prevent leakage current, the following problem is generated. That is, the Ta2O5 layer has a large reaction with the lower electrode formed of a polysilicon layer. Therefore, in a oxidizing process of the substitutional Ta atoms, a natural oxide layer having low dielectric constant between the Ta2O5 layer and the lower electrode. Oxygen moves to an interface between the Ta2O5 layer and the lower electrode, thereby deteriorating the homogeneity of the interface.
Moreover, impurities such as carbon atoms (C), carbon compounds(CH4, C2H4), and H2O are generated inside the Ta2O5 layer by a reaction of organic substances of Ta(OC2H5)5 used as a precursor and O2 (or N2O) gas. These impurities increase leakage current of a capacitor and deteriorate a dielectric property inside the Ta2O5 layer. Therefore, a great capacitor is difficult to obtain.
Meanwhile, the TiN layer 23 also serving as the conductive barrier between the upper electrode 24 and the Ta2O5 layer 22 has the following problems.
First, in case the TiN layer 23 serving as the conductive barrier is formed according to the LPCVD method, the problem is described. TiCl4 gas and NH3 gas are generally used for source gas of the TiN layer formed according to the LPCVD method. At this time, TiCl4 gas has a property of being dissociated at a high temperature of more than 600xc2x0 C. Therefore, the TiN layer is actually formed at much higher temperature than 600xc2x0 C. to control easily Cl density therein. However, when forming the TiN layer, a high temperature process is accompanied, thereby generating mutual diffusion between atoms composing the Ta2O5 layer 22 and the lower electrode 20. And, a gas phase reaction is active in a chamber by NH4 gas having a high reaction, thereby generating a large amount of particles inside the Ta2O5 layer or on the surface thereof. As a result, the homogeneity of the dielectric layer is deteriorated.
Furthermore, when the TiN layer is formed, the amount of Cl inside the TiN layer is difficult to be controlled. As a result, a large amount of Cl inside the TiN layer remain. The TiN layer which a large amount of Cl remained therein is difficult to serve as the conductive barrier, thereby generating leakage current inside the capacitor.
And, since the TiN layer 23 formed of according to the sputtering method has a poor step coverage property, the TiN layer is difficult to be deposited on the upper part of the Ta2O5 layer 22 to the thickness of 200 to 400 xc3x85. As a result, voids are formed between the grains of the HSG layer 21, thereby deteriorating a capacitor property.
In addition, the TiN layer 23 and Ta2O5 layer 22 react at a temperature of 687 K (414xc2x0 C.) as follows.
5TIN+2Ta2O5xe2x86x925TiO2+4TaN+xc2xdN2
That is, in a range of 687 K temperature, the TiN layer 23 and the Ta2O5 layer 24 react, thereby generating undesired TiO2 dielectric substances(not shown) on the interface between the TiN layer 23 and Ta2O5 layer 22. The TiO2 dielectric substances increase the thickness of the dielectric layer, thereby deteriorating capacitance. In addition, TiO2 itself has a high leakage property, thereby increasing leakage current of the dielectric layer.
Accordingly, it is an object of the present invention to improve the uniformity of the dielectric layer by preventing a natural oxide layer from generating between a lower electrode and a Ta2O5 layer.
And, it is another object of the present invention to ensure high capacitance as well as low leakage current.
It is the other object to form a conductive barrier having a good step coverage property.
To achieve the objects according to one aspect of the present invention, a capacitor for a semiconductor memory device includes: a lower electrode; a silicon nitride layer for restraint of a natural oxide layer formed on the lower electrode surface; a dielectric layer formed on the upper part of the silicon nitride layer; and an upper electrode formed on the upper part of the dielectric layer, wherein the dielectric layer is a Ta2O5 layer.
And, according to another embodiment, a capacitor for a semiconductor memory device includes: a lower electrode; a silicon nitride layer for restraint of a natural oxide layer formed on the lower electrode surface; a dielectric layer formed on the upper part of the silicon nitride layer; a conductive barrier made of the silicon nitride layer formed on the dielectric layer surface; and an upper electrode formed on the upper part of the conductive barrier, wherein the dielectric layer is a Ta2O5 layer.
Further, according to the other aspect a method for forming a capacitor for a semiconductor device includes the steps of: forming a lower electrode on the semiconductor substrate; nitride-treating the surface of the lower electrode; depositing the Ta2O5 layer as the dielectric layer on the upper part of the surface nitride-treated lower electrode; and forming an upper electrode on the upper part of the dielectric layer.
Moreover, according to another embodiment of the present invention the method of forming a capacitor for a semiconductor device including the steps of: forming a lower electrode on the semiconductor substrate; nitride-treating the surface of the lower electrode so as to prevent a natural oxide layer from generating on the surface thereof; forming a Ta2O5 layer as a dielectric layer on the upper part of the lower electrode; forming a conductive barrier made of the silicon nitride layer on the upper part of the Ta2O5 layer; and forming an upper electrode on the upper part of the conductive barrier.
And, according to the other embodiment a method of forming a capacitor for a semiconductor device includes the steps of: forming a lower electrode on the semiconductor substrate; nitride-treating the surface of the lower electrode inside a chamber maintaining NH3 or N2/H2 plasma gas and a temperature of 200 to 700xc2x0 C. so as to prevent a natural oxide layer from generating on the surface thereof; forming a Ta2O5 layer as a dielectric layer on the upper part of the lower electrode; crystallizing the Ta2O5 layer after thermal-treatment thereof; forming a conductive barrier made of the silicon nitride layer on the upper part of the Ta2O5 layer in a chamber maintaining plasma gas containing nitrogen and a temperature of 200 to 400xc2x0 C.; and forming an upper electrode on the upper part of the conductive barrier, wherein the surface nitride treatment step of the lower electrode, the formation step of the Ta2O5 layer, the thermal-treating and then crystallizing step of the Ta2O5 layer and the formation step of the conductive barrier are performed in situ in the same chamber.